A perception model that runs well on a workstation faces a harder test once it goes into a real robot. It suddenly needs to run on a small, power-limited processor, and every wasted watt becomes heat the machine needs to deal with. The processing also has to keep pace with the physical world as it happens. Hellbender builds for that environment, and in a recent joint webinar the Pittsburgh perception and manufacturing company explained how it uses Ambarella’s edge AI platform to get there.
Hellbender designs and manufactures perception, edge AI, and robotics components, and it does all of it under one roof in Pittsburgh. Because the company handles every stage, from a product requirements document through proof of concept, validation testing, and full production, it sees the cost of a silicon decision across the whole product lifecycle, well past the benchmark stage. That full-lifecycle view shaped how the company talked about cost in the webinar.
Cost is more than the price of the chip
Most hardware conversations focus on unit cost, the bill of materials for the silicon and the board around it, but Hellbender argued that two other costs matter just as much. One is integration cost, the engineering time spent getting models compiled, debugged, and running on a given processor. The other, adaptability cost, tends to become an issue later. It is the non-recurring engineering effort and the schedule delay a team faces when a chip cannot support a new model architecture and the design has to be redone in both hardware and software. As the Hellbender team put it, the most expensive chip can be the low-BOM processor that forces a full redo the following year.
The architecture question behind physical AI
Perception has been shifting from convolutional networks toward transformer-based models, and the effect of that shift goes beyond accuracy. Transformers rely on operations such as dynamic attention, positional encodings, and dynamic tensor indexing, and those operations do not work well with silicon designed only for fixed-function convolution. When the hardware cannot run them natively, teams write workarounds by hand or accept lower accuracy, and the adaptability cost increases as a result.
That flexibility is why Hellbender put Ambarella silicon at the center of its perception work. Physical AI leans heavily on the newer operator set, whether the task is dense 3D reconstruction, a vision transformer, an on-device vision language model, or one of the vision-language-action architectures now emerging in robotics. A processor that keeps up as models change lets a robotics team design a board today without stranding it against next year’s model.
Efficiency is a whole-system problem
Power efficiency is important for reasons that go beyond battery life. Silicon that wastes power produces more heat, and getting rid of that heat means adding thermal mass. The heavier the heatsink, the larger the motors and batteries the machine needs to carry it, which has an effect on payload and reduces flight or run time. In an untethered robot or a drone, an inefficient processor ends up shaping the size and capability of the entire machine, so performance per watt becomes a system-level constraint that engineers must account for.
What ran in the demo
Running on an Ambarella N1 processor, a high-throughput engine built for large-memory workloads such as LLMs and vision language models, Hellbender showed several perception models working simultaneously in real time, including object detection, depth, optical flow, and an overhead map, together with live vision language model queries run against the scene on the device itself. The perception happened locally, next to the sensor, which is what an edge platform for physical AI is meant to do. Ambarella’s compact CV-series processors cover the lower-power end of the same family, built for computer vision and safety-critical real-time loops.
For teams that would rather not start from a blank compiler, Hellbender pointed to Ambarella’s Developer Zone for onboarding. The DevZone provides a library of models already quantized and optimized for specific Ambarella chips, which lets a developer evaluate options and benchmark throughput, power draw, and memory against real targets before committing to a board layout. The Hellbender team also described compiling frontier models directly from PyTorch and ONNX, including recent systems such as DINOv3 and DepthAnything3, and using the platform’s mixed-precision and optimization tooling to hold accuracy while improving efficiency on live systems. Those figures come from Hellbender’s own production work.
Watch the webinar
One key takeaway from the session is that a processor should be judged on how well it will handle the models a team has not built yet. For its own robotics work, that reasoning led Hellbender to Ambarella’s platform. Check out the webinar here.