Ambarella is a fabless semiconductor company headquartered in Santa Clara, CA with offices in Hsinchu, Taiwan, Hong Kong and Shanghai, China.

* Verification Engineer (job#95603)
Location : Santa Clara, CA
Job Description :
Responsible for
• Develop Testbenches for DSP logic blocks, processor cores, coprocessor cores and other digital logic devices in SystemVerilog, C and C++.
• Write test plans for the above mentioned DUT-s
• Write and debug tests for the above-mentioned DUT-s using SystemVerilog, Perl, Assembly,C, C++ and possibly other languages. Write Random Test Generators to automatically generate most of the tests. Write coverage monitors to evaluate the coverage of the DUT-s
• Write system level tests for Ambarella’s chips
• Participate in chip bringup.
Requirements :
• The successful candidate possesses a master’s degree in EE or CS.
• Versatile and skilled both in Verilog/SystemVerilog as well as C/C++/Perl and Assembly.
• Strong communication skills and is a strong team player.

* ASIC Design Engineer (job#95701)
Location : Santa Clara, CA
Job Description :
• Involved in ASIC development flow.
• Understand system level requirement and generate hardware spec.
• Logic design using Verilog HDL.
• Synthesize logic into gate netlist with tools.
• Perform timing analysis, and close timing issue.
• Verify and debug functionality.
• Lab bring-up and debugging.
Requirements :
• Strong logic design skill.
• Familiar with Verilog HDL.
• Typically requires MSEE with related work experience.

To apply please submit resume to jobs@ambarella.com